Power consumption is becoming an increasing concern in the design of integrated circuits (ICs), particularly for very large scale integration (VLSI) chip design. Increases in power consumption are outpacing the advantages of advances in scaling in silicon technologies, and the benefits of reducing power supply voltages. Power management has been recognized as an important consideration associated with the design and operation of VLSI (Very Large Scale Integration) chips to mitigate power consumption associated with VLSI chips. For example, power consumption is becoming a serious performance limiter for high speed microprocessors. For instance, a key design objective for microprocessor systems is providing the highest possible peak performance for computer-intensive code, while reducing power consumption of the microprocessor system.
As a result, power management systems have been employed that vary processor frequency and/or supply voltage in order to hold the power consumption of a chip below a certain level that is acceptable for use in a given system (e.g., within a desktop, workstation or portable devices). However, power management systems do not take into consideration variations that can affect application performance across different systems.